HDD and other storage devices connectors
M.2 (Next Generation Form Factor, NGFF), is a specification for computer expansion cards. Having a small and flexible physical specification, the M.2 is suitable for solid-state storage applications, especially when used in small devices such as ultrabooks or tablets.

The M.2 standard is designed as a revision and improvement to the mSATA standard, which uses the PCI Express Mini Card physical layout. While mSATA took advantage of the existing PCI Express Mini Card form factor and connector, M.2 has been designed to maximize usage of the card space.  Supported host controller interfaces and internally provided ports are a superset to those defined by the SATA Express interface. M.2 modules can integrate multiple functions, including the following device classes: Wi-Fi, Bluetooth, satellite navigation, near field communication (NFC), digital radio, Wireless Gigabit Alliance (WiGig), wireless WAN (WWAN), and solid-state drives (SSDs).

Computer bus interfaces provided through the M.2 connector are PCI Express 3.0 (up to four lanes), Serial ATA 3.0, and USB 3.0 (a single logical port for each of the latter two). It is up to the manufacturer of the M.2 host or device to select which interfaces are to be supported, depending on the desired level of host support and device type. The M.2 connector has different keying notches that denote various purposes and capabilities of M.2 hosts and modules, preventing plugging of M.2 modules into feature-incompatible host connectors

M.2 uses a dual-sided edge card connector with a 0.5 mm contact pitch. There are some mechanical keys defined for SSDs.  For example key B M.2 pinout supports SSD/WWAN: 1x SATA SSD or 1x, 2x PCIe SSD (and WWAN) Host Interfaces. Key M M.2 pinout supports SSDs only: 1x SATA or 1x, 2x, or 4x PCIe Host Interfaces. Sockets are defined as follows:  Socket 1 accepts cards with an “A” key notch present, Socket 2 accepts cards with a “B” key notch present, Socket 3 accepts cards with an “M” key notch present.

M.2 pinout for key B (1x SATA, 2x PCIe)

Pin
Number
Pin
Name
Description
1 CONFIG_3   Defines module type
2 3.3 V  Supply pin, 3.3 V
3 GND   Ground
4 3.3 V   Supply pin, 3.3 V
5 N/C   
6-8 N/A   
9 N/C   
10 DAS/DSS   Device Activity Signal / Disable Staggered Spinup
11 N/C   
12-19 removed  Mechanical notch B
20 N/A   
21 CONFIG_0   Defines module type
22-26 N/A   
27 GND   Ground
28 N/A   
29 PERn1   PCIe Lane 1 Rx
30 N/A   
31  PERp1   PCIe Lane 1 Rx
32 N/A   
33 GND   Ground
34 N/A   
35 PETn1   PCIe Lane 1 Tx
36 N/A   
37 PETp1   PCIe Lane 1 Tx
38 DEVSLP  Device Sleep, input. If driven high the host is informing the
SSD to enter a low power state.
39 GND   Ground
40 N/A   
41 SATA-B+/PERn0  Host receiver differential signal pair. If in PCIe mode PCIe Lane 0 Rx
42 N/A   
43 SATA-B-/PERp0  Host receiver differential signal pair. If in PCIe mode PCIe Lane 0 Rx
44 N/A   
45 GND   Ground
46 N/A   
47 SATA-A-/PETn0  Host transmitter differential signal pair. If in PCIe mode PCIe Lane 0 Tx
48 N/A   
49 SATA-A+/PETp0   Host transmitter differential signal pair. If in PCIe mode PCIe Lane 0 Tx
50 PERST#   PCIe reset
51 GND   Ground
52 CLKREQ#   Reference clock request signal
53 REFCLKN   PCIe Reference Clock signals (100 MHz)
54 PEWAKE#   PCIe WAKE# Open Drain with pull up on platform. Active Low.
55 REFCLKP   PCIe Reference Clock signals (100 MHz)
56 MFG1  Manufacturing pin. Use determined by vendor.
57 GND   Ground
58 MFG2  Manufacturing pin. Use determined by vendor.
59-66 removed   Mechanical notch M
67 N/A   
68 SUSCLK   32.768 kHz clock supply input provided by the Platform chipset
69 CONFIG_1  Defines module type
70 3.3 V   Supply pin, 3.3 V
71 GND  Ground
72 3.3 V  Supply pin, 3.3 V
73 GND  Ground
74 3.3 V  Supply pin, 3.3 V
75 CONFIG_2 Defines module type

 

CONFIG pins are set by the SSD to inform the host if the drive wishes to use the
SATA or PCIe signaling scheme. SSD-SATA pull pin 1, pin 21, pin 69, pin 75 to Ground.
 

M.2 pinout for key M (1x SATA, 1x, 2x, or 4x PCIe)

Pin
Number
Pin
Name
Description
1 CONFIG_3   Defines module type
2 3.3 V  Supply pin, 3.3 V
3 GND   Ground
4 3.3 V   Supply pin, 3.3 V
5 PERn3   PCIe Lane 3 Rx
6 N/A   
7 PERp3  PCIe Lane 3 Rx
8 N/A  
9 GND   Ground
10 DAS/DSS   Device Activity Signal / Disable Staggered Spinup
11 PETn3   PCIe Lane 3 Tx
12 3.3 V  Supply pin, 3.3 V
13 PETp3  PCIe Lane 3 Tx
14 3.3 V  Supply pin, 3.3 V
15 GND  Ground
16 3.3V  Supply pin, 3.3 V
17 PERn2 PCIe Lane 2 Rx
18 3.3 V  Supply pin, 3.3 V
19 PERp2 PCIe Lane 2 Rx
20 N/A   
21 CONFIG_0   Defines module type
22 N/A   
23 PETn2  PCIe Lane 2 Tx
24 N/A  
25 PETp2  PCIe Lane 2 Tx
26 N/A  
27 GND   Ground
28 N/A   
29 PERn1   PCIe Lane 1 Rx
30 N/A   
31 PERp1   PCIe Lane 1 Rx
32 N/A   
33 GND   Ground
34 N/A   
35 PETn1   PCIe Lane 1 Tx
36 N/A   
37 PETp1   PCIe Lane 1 Tx
38 DEVSLP  Device Sleep, input. If driven high the host is informing the
SSD to enter a low power state.
39 GND   Ground
40 N/A   
41 SATA-B+/PERn0  Host receiver differential signal pair. If in PCIe mode PCIe Lane 0 Rx
42 N/A   
43 SATA-B-/PERp0  Host receiver differential signal pair. If in PCIe mode PCIe Lane 0 Rx
44 N/A   
45 GND   Ground
46 N/A   
47 SATA-A-/PETn0  Host transmitter differential signal pair. If in PCIe mode PCIe Lane 0 Tx
48 N/A   
49 SATA-A+/PETp0   Host transmitter differential signal pair. If in PCIe mode PCIe Lane 0 Tx
50 PERST#   PCIe reset
51 GND   Ground
52 CLKREQ#   Reference clock request signal
53 REFCLKN   PCIe Reference Clock signals (100 MHz)
54 PEWAKE#   PCIe WAKE# Open Drain with pull up on platform. Active Low.
55 REFCLKP   PCIe Reference Clock signals (100 MHz)
56 MFG1  Manufacturing pin. Use determined by vendor.
57 GND   Ground
58 MFG2  Manufacturing pin. Use determined by vendor.
59-66 removed   Mechanical notch M
67 N/A   
68 SUSCLK   32.768 kHz clock supply input provided by the Platform chipset
69 CONFIG_1  Defines module type
70 3.3 V   Supply pin, 3.3 V
71 GND  Ground
72 3.3 V Supply pin, 3.3 V
73 GND  Ground
74 3.3 V Supply pin, 3.3 V
75 CONFIG_2 Defines module type

 

M.2 module keying

Key
ID
Notched
pins
Provided interfaces
A 8–15 PCIe ×2, USB 2.0, I2C and DP ×4
B 12–19 PCIe ×2, SATA, USB 2.0 and 3.0, audio, UIM, HSIC, SSIC, I2C and SMBus
E 24–31 PCIe ×2, USB 2.0, I2C, SDIO, UART and PCM
M 59–66 PCIe ×4, SATA and SMBus

 

75 pin M.2 Edge (B and M notched) connector layout
75 pin M.2 Edge (B and M notched) connector
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Source(s) of this and additional information: Serial ATA Revision 3.2 Gold
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