| Pin Number |
Pin Name |
Description |
|---|---|---|
| 1 | A0 | Processor address bus pin 0 |
| 2 | D0 | Processor data bus pin 0 |
| 3 | A1 | Processor address bus pin 1 |
| 4 | D1 | Processor data bus pin 1 |
| 5 | A2 | Processor address bus pin 2 |
| 6 | D2 | Processor data bus pin 2 |
| 7 | A3 | Processor address bus pin 3 |
| 8 | D3 | Processor data bus pin 3 |
| 9 | A4 | Processor address bus pin 4 |
| 10 | D4 | Processor data bus pin 4 |
| 11 | A5 | Processor address bus pin 5 |
| 12 | D5 | Processor data bus pin 5 |
| 13 | A6 | Processor address bus pin 6 |
| 14 | D6 | Processor data bus pin 6 |
| 15 | A7 | Processor address bus pin 7 |
| 16 | D7 | Processor data bus pin 7 |
| 17 | A8 | Processor address bus pin 8 |
| 18 | EX0 | Extra pin for future use or for communication between expansion cards |
| 19 | A9 | Processor address bus pin 9 |
| 20 | EX1 | Extra pin for future use or for communication between expansion cards |
| 21 | A10 | Processor address bus pin 10 |
| 22 | SLW | Used by slow peripherals to request a slower clock speed, active low. |
| 23 | GND | Ground |
| 24 | VCC | Positive voltage |
| 25 | VCC | Positive voltage |
| 26 | GND | Ground |
| 27 | A11 | Processor address bus pin 11 |
| 28 | SS | An expansion card is selected. Used by the processor card to disable it's built-in ram and ROM, active low |
| 29 | A12 | Processor address bus pin 12 |
| 30 | INH | When this is active (low), processor card RAM and ROM are disabled |
| 31 | A13 | Processor address bus pin 13 |
| 32 | SEL | Used by the backplane to signal to expansion cards when they should activate, active low |
| 33 | A14 | Processor address bus pin 14 |
| 34 | L1 | Connected to one of the backplane LEDs |
| 35 | A15 | Processor address bus pin 15 |
| 36 | L2 | Connected to one of the backplane LEDs |
| 37 | RDY | Processor I/O pin. When low, the processor waits in it's curent state |
| 38 | L3 | Connected to one of the backplane LEDs |
| 39 | BE | Processor input pin. when low the processor releases the bus |
| 40 | L4 | Connected to one of the backplane LEDs |
| 41 | CLK | Main computer clock. Can be stretched or not depending on the state of the SLOW signal. |
| 42 | CLK_12M | Stable clock for e.g. VIA timers. Not connected to slot 0 |
| 43 | R/W | CPU read / write pin |
| 44 | EX2 | Extra signal 2. Not connected to slot 0 |
| 45 | IRQ | This goes low when an interrupt request has occured, active low |
| 46 | EX3 | Extra signal 3. Not connected to slot 0 |
| 47 | SYNC | CPU output. Indicates when the CPU is fetching an opcode |
| 48 | SIRQ | Used by expansion cards to signal an interrupt request to the processor board, active low |
| 49 | RST | Reset signal trigered by the button on the backplane, active low |
| 50 | NMI | non maskable interrupt signal trigered by the button on the backplane, active low |


