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8 pins connector
Pin Name Direction Description
1 TCK Test Clock
2 GND Ground
3 TDI Test Data Input
4 GND Ground
5 TDO Test Data Output
6 VCC Power Supply
7 TMS Test Mode Select
8 TRS Test Reset

 

Pinout status: +2 -0
According to 2 reports in our database (2 positive and 0 negative) the JTAG Header for FPGA/CPLD Applications (Comcom Electronics Standard) pinout should be correct.

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JTAG Header for FPGA/CPLD Applications (Comcom Electronics Standard) visual pinout:click to enlarge
Source(s) of this and additional information: www.comcom.ru and Sandy
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